Digital-to-analog converters, i.e., electronic devices which convert digital binary input to an analog signal for output purposes, such as for data display or the like, have an accuracy barrier which, as a practical matter, limits the number of bits of digital input which can be processed. The accuracy barrier has been attacked by a number of different approaches with the majority of the efforts applied to the standard R/2R ladder configuration with the Herman Schmid switch adaptation. This configuration consists of a plurality of stages, a stage for each bit of information ranging from the most significant bit to the least significant bit, utilizing a transistor switch (FET) as the current switching device. This configuration requires that each successive FET in the configuration have twice the ON resistance of the FET in the previous stage to achieve current balance and temperature drift compensation. As a practical matter, the resolution of monolithic converters employing the R/2R ladder configuration seem to have reached an apparent practical limit of about 12 bits. A 12 bit converter, for example, would require FET geometry variation (between the most significant bit FET and the least significant bit FET) of 2.sup.11, or 1 to 2048. This approach leaves the FET as a major source of difficulty from the standpoint of manufacturing transistors which will accurately have the required geometry and electrical characteristics. In addition, it will be understood that the cost of such converters is directly affected by these requirements.